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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">SCTLR2_EL3, System Control Register (EL3)</h1><p>The SCTLR2_EL3 characteristics are:</p><h2>Purpose</h2>
        <p>Provides top level control of the system, including its memory system, at EL3.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_SCTLR2 is implemented. Otherwise, direct accesses to SCTLR2_EL3 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>SCTLR2_EL3 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_5">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="27"><a href="#fieldset_0-63_5">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4-1">EnANERR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3-1">EnADERR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1-1">EMEC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-63_5">Bits [63:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_4-1">EnANERR, bit [4]<span class="condition"><br/>When FEAT_ANERR is implemented:
                        </span></h4><div class="field">
      <p>Enable Asynchronous Normal Read Error.</p>
    <table class="valuetable"><tr><th>EnANERR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>External abort on Normal memory reads generate synchronous Data Abort exceptions in the EL3 translation regime.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>External abort on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime.</p>
        </td></tr></table><p>It is implementation-specific whether this field applies to memory reads generated by each of the following:</p>
<ul>
<li>SVE register loads, when <span class="xref">FEAT_SME</span> is implemented and the PE is in Streaming SVE mode.
</li><li>SME register loads.
</li><li>LD&lt;op&gt;, SWP and CAS{P} Atomic instructions that return a value to the PE.
</li><li>ST64BV{0} instructions that return a value to the PE.
</li><li>RCW instructions that return a value to the PE.
</li></ul>
<p>Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.</p>
<p>Setting this field to 0 might have a performance impact for Normal memory reads.</p>
<p>This field is ignored by the PE and treated as one when all of the following are true:</p>
<ul>
<li><span class="xref">FEAT_ADERR</span> is implemented.
</li><li><a href="AArch64-id_aa64mmfr3_el1.html">ID_AA64MMFR3_EL1</a>.ANERR reads as <span class="binarynumber">0b0010</span>.
</li><li>SCTLR2_EL3.EnADERR is 1.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-4_4-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-3_3-1">EnADERR, bit [3]<span class="condition"><br/>When FEAT_ADERR is implemented:
                        </span></h4><div class="field">
      <p>Enable Asynchronous Device Read Error.</p>
    <table class="valuetable"><tr><th>EnADERR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>External abort on Device memory reads generate synchronous Data Abort exceptions in the EL3 translation regime.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>External abort on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime.</p>
        </td></tr></table><p>It is implementation-specific whether this field applies to memory reads generated by each of the following:</p>
<ul>
<li>FP&amp;SIMD register loads.
</li><li>SVE register loads.
</li><li>SME register loads.
</li><li>LD&lt;op&gt;, SWP and CAS{P} Atomic instructions that return a value to the PE.
</li><li>ST64BV{0} instructions that return a value to the PE.
</li><li>RCW instructions that return a value to the PE.
</li></ul>
<p>Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.</p>
<p>Setting this field to 0 might have a performance impact for Device memory reads.</p>
<p>This field is ignored by the PE and treated as one when all of the following are true:</p>
<ul>
<li><span class="xref">FEAT_ANERR</span> is implemented.
</li><li><a href="AArch64-id_aa64mmfr3_el1.html">ID_AA64MMFR3_EL1</a>.ADERR reads as <span class="binarynumber">0b0010</span>.
</li><li>SCTLR2_EL3.EnANERR is 1.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-3_3-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-2_2">Bit [2]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-1_1-1">EMEC, bit [1]<span class="condition"><br/>When FEAT_MEC is implemented:
                        </span></h4><div class="field">
      <p>Enables MEC for the Realm physical address space at EL3.</p>
    <table class="valuetable"><tr><th>EMEC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>MEC is not enabled for the Realm physical address space at EL3.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>MEC is enabled for the Realm physical address space at EL3.</p>
        </td></tr></table>
      <p>This bit is permitted to be cached in a TLB.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-1_1-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0">Bit [0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing SCTLR2_EL3</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, SCTLR2_EL3</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b110</td><td>0b0001</td><td>0b0000</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    X[t, 64] = SCTLR2_EL3;
                </p><h4 class="assembler">MSR SCTLR2_EL3, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b110</td><td>0b0001</td><td>0b0000</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    SCTLR2_EL3 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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